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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. august 2007 rev 3 1/44 44 STE12PS 12 channel integrated pse line manager features pse power control device supports up to 12 independent, 4 (a) or 6 (b) 30w ?boosted? ports wide operating range: up to 90v ieee 802.3af compliant open circuit detection: ac and dc methods advanced power management algorithm current sensing with as low as 500m , external, series resistors no need for external fets in-rush current control short-circuit protection adaptable signature detection capability on-chip 3.3v smps controller low-noise, 12-bit adc standard i 2 c interface parallel monitor interface description STE12PS is designed to supply power over multiple ethernet channels in order to avoid different, individual power supply units for applications such as web cams, ip phones, bluetooth access points and wlan access points. the equipment that provides the power to the twisted pair cabling is referred to as power sourcing equipment (pse). the pse?s main functions are: looking for links to a powered device (pd), classifying a pd, supplying power to the link, monitoring power on the link, and removing power from the link. the STE12PS is fully programmable, supporting the detection and powering of ieee802.3af as well as legacy pds. the flexibility of the STE12PS allows the user to select a suitable system configuration: up to 12 ports as well as 4 (a) or 6 (b) ?boosted? channels. if needed, the STE12PS can also efficiently manage cases or applications where a limited amount of power is available to the ports (smart-power capability) by means of integrated, power mosfet devices. all operations are controlled via the i 2 c bus also notifying externally some ports status condition via dedicated pins. ethernet port isolation can be easily maintained thanks to an integrated 3.3v smps power source and by means of optocouplers. the STE12PS has five address selection inputs to choose up to 32 possible different addresses. power can be provided to the pd using either spare lines of the ethernet cable or using the data wires, as specified by ieee 802.3af. a. in auto mode b. in manual mode pbga23x23 pbga23x23 www.st.com obsolete product(s) - obsolete product(s)
contents STE12PS 2/44 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 detection and classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1 detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.2 classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.3 detection and classification fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 under load (disconnection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 short circuit, overload and overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 thermal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 internal 3.3v/10v generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 6mhz clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 smart-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 power boost mode - 30w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8.1 four channels in auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8.2 six channels in manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 measurement and parameter codings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 i2c slave protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 i2c device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 register addressing: write command format . . . . . . . . . . . . . . . . . . . . . . 28 5.6 register addressing: read command format . . . . . . . . . . . . . . . . . . . . . . 29 5.7 parallel monitoring interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 obsolete product(s) - obsolete product(s)
STE12PS contents 3/44 6 electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 ball coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 package information - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 41 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 obsolete product(s) - obsolete product(s)
block diagram STE12PS 4/44 1 block diagram figure 1. STE12PS functional block diagram figure 2. typical application diagram 12 x power switches analog front end power-on control inrush current limiting internal clock generator ac disconnect generator & detector 50hz ~ i 2 c interface monitoring output interface smart power & port priority management programmable detection/ classification digital controller line detection classification monitoring tri-level temperature protection 3.3v smps controller 12-bit adc programmable timer settings 12 x power switches analog front end power-on control inrush current limiting internal clock generator ac disconnect generator & detector 50hz ~ i 2 c interface monitoring output interface smart power & port priority management programmable detection/ classification digital controller line detection classification monitoring tri-level temperature protection 3.3v smps controller 12-bit adc programmable timer settings to opto coupler s s te12p s 3 . 3 v to other device s i2c_addrx s clin s dain s daout intn i 2 c bu s f s rpx ss rpx hqgnd rmon s rmonf ac s x s px s mp s _vl rlim vdrive px v 3 _ 3 +4 8 v d1 x 12 d2 x 12 r s en s e x12 rmon r1 r2 r 3 d 3 d4 c1 c2 l1 r2 r 3 d 3 d4 c1 c2 l1 low co s t pmo s vl gnd s s mp s _gnd clkgenx c 3 x12 c4 c5 obsolete product(s) - obsolete product(s)
STE12PS pin description 5/44 2 pin description table 1. analog pins description pin name i/o function idet_hvlv o anti-aliasing filter capacitor to be connected between the analog input and ground to improve adc noise performance. c = 180pf. imon_hvlv o anti-aliasing filter capacitor to be connected between the analog input and ground. c = 180pf. vbat_mon o anti-aliasing filter capacitor to be connected between the analog input and ground. c = 100nf. vbatref o anti-aliasing filter capacitor to be connected between the analog input and ground. c = 100nf. i_ref o anti-aliasing filter capacitor to be connected between the analog input and ground. c = 180pf. cdetslow o detection rise/fall time capacitor (up to 25nf). tr/f can be set from 1ns to 4ms. rsense o smps precision, external, current limiting reference resistor: 100m vdrive o external p-channel mosfet gate driving voltage for smps. it provides a square wave with vl as upper limit and (vl-10v) as lower limit voltage. sftstr o switched mode power supply (smps) soft start capacitor, 200nf. fb io smps feedback pin, cfb = 2.2nf pn o power dmos device drain, if dmos is turned-on, channel ?n? where n = 1,?12 is activated. acsn o it provides a 50hz ac disconnection signal for port ?n?, n = 1, ? 12. spn i detection classification and ac disconnection sensing port ?n?, n = 1, ? 12. ssrpn i line current to the monitoring resistor for channel ?n?, n = 1,? 12. allowed values are 0.523, 1.05, 1.58 and 2.1ohms (see also sensprog preset pins). sensing pin. fsrpn o source terminal for power dmos connected to the sense resistor for channel ?n?, n = 1,? 12, a ?forcing? pin. rmonf o mirror monitoring resistance (500 r sense ) pin to let internal adc evaluate line currents. forcing pin. rmons o mirror monitoring resistance (500 r sense ) pin to let internal adc evaluate line currents. a ?sensing? pin. rref i reference bias resistor: 18.7k ? clk_gen1 i crystal oscillator pin1 for high performance clock generation. clk_gen2 i crystal oscillator pin2 for high performance clock generation. mclk o master clock output for multi device configuration. clk_gen3 i low profile clock input pin or clock input pin in multi-device configuration. acin i 50hz sinusoidal input acout o 50hz sinusoidal output, internally generated obsolete product(s) - obsolete product(s)
pin description STE12PS 6/44 table 2. digital pins description pin name i/o function reset resetn i reset pin. active low status flag interface ch_seln o channel identification ?n?, where n = 1,? 12. indicates the channel whose status flags (pok, ?) are currently notified externally. ch_sel is incremented every 60 * mclk clock cycles. the status flag notification is enabled via the configuration register global_cfg2, status_flag_en bit. pok o power ok flag. this flag indicates condition of the currently powered channel: ?1? power on and no faults are present ?0? power off or (power on and faults present) ovld o overload alarm flag for the currently powered channel. current overload condition (icut is over threshold): ?1? channel overload condition detected ?0? no overload ovcur o short circuit alarm flag for the currently powered channel. current limiting condition: ?1? overcurrent or detection failed condition detected ?0? any short circuit condition detected ac_dc_discon o ac/dc disconnection alarm flag for the currently powered channel: ?1? ac/dc disconnection detected ?0? any disconnection detected det_class o detection/classification flag. ?1? detection or classification procedure is running ?0? detection/classification procedure is not running. por_n o ?1? vl, 10v and 3.3v supply power on succeeded thermal monitoring t_monitor x o thermal monitoring (x = 0,1). these bits encode the internal temperature?s threshold measured in the following way: ?00? temperature under 110 c ?01? temperature between the 110 c to 130 c ?11? temperature between the 130 c to 150 c ?10? temperature is above 150 c obsolete product(s) - obsolete product(s)
STE12PS pin description 7/44 configuration signals a_bn_sel i a or b alternative configuration mode select. ?0? alternative b (midspan-pse) ?1? alternative a (endpoint-pse) ch_num x i 12- or 4-boost channel select. x = 0,1. ?00? 12 channels configuration ?01? na ?10? na ?11? 4-boost channel configuration auto_start i auto start mode enable. ?0? auto start mode disabled: all the ports are disabled after reset, neither detection nor power on is performed (mode[1:0] register selected to power down at the reset event) ?1? auto start mode enabled: all the ports are automatically enabled, detection, classification and power are performed (mode[1:0] register selected to auto after the reset event) s/upin i smps (switch mode power supply) mode selector bit (supplier / user). when not connected the device works as dc-dc converter controller. senseprog x i preset pins for sensing resistor programmability (x=0,1). the programmed value must match the mounted r sense resistors. ?00? r sense = 0.5 ? ?01? r sense = 1 ? ?10? r sense = 1.5 ? ?11? r sense = 2 ? power on controller signals power_en x i reserved. (x = 0, ?11). i 2 c signals i2c_addr x i this defines the device address for the i 2 c interface. x = 0, ? 4. sclin i serial clock input pin for the i 2 c interface. sdain i serial data input pin for the i 2 c interface. when ?jumpered? with the sdaout pin, this connection becomes the standard bi-directional serial data line (sda). sdaout o serial data output pin for the i 2 c interface. when jumpered with the sdain pin, this connection becomes the standard bi-directional serial data line (sda). intn o i 2 c open drain output that goes low when interrupt event is notified test mode signals test_mode x i test mode enable (x = 0,1). ?00? functional mode ?01? reserved ?10? reserved ?11? reserved scan_en i reserved. preset to ?0?. table 2. digital pins description (continued) pin name i/o function obsolete product(s) - obsolete product(s)
pin description STE12PS 8/44 table 3. power and ground pins description pin name i/o function gnd, agnd i analog grounds smpsgnd i smps power ground smps_vl i +48v battery voltage for smps v3_3,vdd,vdde i 3.3v supply v10, vdd10 i/o 10v supply to power-up the output dmos and minimize its on resistance hqgnd i dedicated ground for kelvin line current sense resistor (a high quality ground) dgnd, gnd, gnde i digital grounds vl i +48v battery voltage. obsolete product(s) - obsolete product(s)
STE12PS functional description 9/44 3 functional description the STE12PS architecture provides a complete pse interface and smart digital controller to efficiently manage the functions in a poe system. all operations can be controlled through r/w registers via a standard i 2 c bus interface. the STE12PS is designed to control power delivery of up to 12 separate lines. this is performed by controlling 12 integrated, power mos transistors connected to the low side of the line - monitoring the line voltage and sensing line current by means of external, series sensing resistors (one per port). turning on a port means to switch the relative mos transistor thus controlling the inrush current in order to rise the port voltage up to 48v (typical battery voltage) after a valid pd signature has been detected. the flexibility of the STE12PS allows the user to select a suitable system configuration: 12 "standard", 4 or 6 "boosted" 30w channels, by means of pins ch_numn. also, one can select the type of architecture (endpoint pse/ alternative a or midspan pse/alternative b) for all channels via pin a_bn_sel. some typical applications for the STE12PS include : ethernet switches/routers midspan power supplies ip-pbx wlan access points 3.1 operating modes the digital controller can operate in one of five possible modes for all the channels, selectable through the global configuration registers: stand-by, auto, semi auto, manual or power down. when the reset condition is removed, the controller defaults to power down mode if the auto_start pin is tied low; if auto_start is tied high the mode is configured in auto. the mode can be changed only during a limited amount of time (100ms), after the reset is released, accessing the global configuration registers before the detection procedure is started, or placing the device in stand-by mode via the i 2 c interface. the characteristics of the five possible operating modes are described below: stand-by: the controller allows only the read write operations suitable for changing programmability. to enable this mode set the reset bit 1 of the reg0x05. auto: the controller autonomously performs detection, classification and power on command without the need of host commands. a subset of status flags stored in the channels monitor registers is reported externally through the status flag notifies pins allowing operation without the presence of the host controller. semiauto: after a triggering command the controller autonomously performs detection and classification waiting a dedicated command from host processor for the power on. based on the detection and classification results reported in the channels status registers, the host controller can decide to power on the selected channel. the disconnection of a channel is automatic as in the auto mode, unless disabled. manual: any action is performed manually. the host controller has the responsibility to force any state transition in the fsm. then based on the measures performed automatically by the adc on several parameters, the host controller can decide to obsolete product(s) - obsolete product(s)
functional description STE12PS 10/44 classify the channel and afterwards to issue the power on command. the STE12PS controller can also automatically disconnect a channel in fault condition (if not enabled, the STE12PS will notify automatically only a short circuit condition or an ac disconnection event. overload or dc disconnection is responsibility of the host controller.) the host controller can also power on a channel skipping detection and/or classification procedures. power down: the controller is put in power down state. no actions are performed until the power down mode is removed. for all operating modes, except power-down and stand-by, the power on/off condition of each channel can also be managed, directly, by the host processor or controller via a dedicated command. moreover, the power removal procedure is performed automatically (also in manual mode) when a fault event has been detected (ac/dc disconnection, overload or overcurrent); this behavior can be changed configuring appropriately some dedicated enable/disable bits of channels event registers. with priority management in auto mode and smart-power management enabled, it is also possible to set different priorities for different channels. the STE12PS will probe channels starting from those with the highest priority . in case of a shortage of available power, it is also possible to disable powering of newly detected, lower priority ports until the highest detected ones are served. 3.2 detection and classification 3.2.1 detection the STE12PS looks for, in turn on the free available ports (according to the priority list if enabled ) , for a valid pd signature (25k slope characteristic) by driving two different voltage levels at the port ( 4v and 8v ) , and calculating the slope resistance/ conductance by monitoring the current difference . the equivalent circuit for the ieee802.3af detection phase is shown in figure 3 below. figure 3. ieee802.3af detection circuit as detection is performed by multiplexing a common voltage generator. if more than one port is connected to several pds, an extra delay in the detection start will be introduced. see table 12: electrical characteristics , parameter tdetd. + d2 p+ p- zsource v _ + d2 p+ p- zsource v d1 d2 p+ p- zsource v _ pc00103 d1(one per port) is external. d2 (one per port) external is required only if the ac_disconnection function is used, otherwise it is internally emulated. obsolete product(s) - obsolete product(s)
STE12PS functional description 11/44 by default, the STE12PS will recognize a valid signature with the following characteristics: ? an inverse slope of the port current vs. voltage (i-v) characteristic measuring between 19 and 26.5k ? (rdl and rdh), ? a port capacitance of less than 4f. if required, the STE12PS can also perform a custom, resistive detection search ? modifying the acceptance window. this can be easily performed by changing the rdh and rdl limits or by changing gdl and gdh via the logic interface. in midspan applications, where power is applied via spare wires, when the pse fails to detect a pd, the port remains in high-impedance (hi-z) for at least two seconds. if the signature resistance is greater than 500k ? , then the two second wait is avoided. transition rates of the port voltage between the two probing levels can be adjusted with capacitance cdetslow. 3.2.2 classification once a valid signature is detected, the port is probed for classification in order to perform smart-power management (if enabled). port probing is performed by forcing a dc voltage in the range of 16v to 18v (one dc generator multiplexed between the channels) and monitoring current i class . the measurement is repeated and stored in the channel monitor classification registers to ensure a coherent classification. the pd power class is defined as shown in ta b l e 4 above. the detected class is then stored in the channel status registers. note: the power absorbed in a link is calculated considering the actual value of the battery voltage in order to arrive at a true power measurement result. table 4. pd power classification class usage maximum power level at pse output (pall) power level at pd input i class 0 default 15.4w (programmable) 0.44 to 12.95w i class < ithcl0 1 optional 4w (programmable) 0.44 to 3.84w ithcl0 < i class < ithcl1 2 optional 7w (programmable) 3.84 to 6.49w ithcl1< i class < ithcl2 3 optional 15.4w (programmable) 6.49 to 12.95w ithcl2 < i class < ithcl3 4 optional - reserved ithcl3 < i class < ithcl4 0 default 15.4w (programmable) 0.44 to 12.95w ithcl4 < i class obsolete product(s) - obsolete product(s)
functional description STE12PS 12/44 3.2.3 detection and classification fsm this fsm manages all operations related to the detection and classification procedures. for these two procedures, the following assumptions are made: 1. a channel is detected only if: a) the channel has not yet been detected, and channel detection has been enabled, and b) the backoff detection timer and subsequent attempt timer are not running (after a corresponding fault detection or failed signature). 2. a channel is classified only if: a) channel classification is enabled, and b) the previous related detection procedure has reported an rgood/ggood value (auto and semiauto modes). three general macro operations can be performed: startup: the following operations are related to the startup procedure: ? reset: reset and initialize all digital aspects of the STE12PS, ? wait_power_up: wait 100ms for completion of the power-up procedure. during this period, the i 2 c bus is active - allowing the host to initialize registers while the detection procedure is waiting to start. ? detection start: all setting-up needed to start operations is performed in this state. the first battery voltage sample is latched in a dedicated register. detection: the following operations are related to the detection procedure for the channel selected: ? low voltage detection command (4v) is issued via registers; detection timer is started to execute the command for a duration of ?tdet ms. ? wait for 5ms to acquire a stable measurement. ? sampled sensing current values are acquired via a/d converter. ? the samples previously acquired are averaged and the resulting value, reported into the channels monitor register, is compared against programmed min/max values. if the sensing current is higher than maximum allowed value, the detection procedure is considered as having failed: backoff timer is started (alternative b) and an alarm flag raised according to the channel status registers. ? if the sensing current results lower than the minimum allowed value the detection procedure is continued: the alarm flag is raised in the channel status registers. ? the described operations are repeated for the high-voltage detection command (8 v). ? signature resistance is calculated: ? if 2sec < gmeas < glow or ghigh < gmeas, then backoff timer is started (alternative b) and detection result failure is reported in the channel status registers. ? else, glow < gmeas < ghigh and the result of a successful detection is reported in the channel status registers. obsolete product(s) - obsolete product(s)
STE12PS functional description 13/44 classification: the following operations are related to the classification procedure for the corresponding channel ? if classification is not enabled, the default class 0 is assigned. ? high voltage detection command (17v) is issued via registers; detection timer is started to execute the command for 15ms duration. ? wait for 5ms to acquire a stable measurement ? sampled sensing current values are acquired via a/d converter. ? average the previously acquired samples and report the resulting value in a dedicated register. the power class is identified and the result is reported in the channel status registers. ? channel is ready to be powered: if the smart-power algorithm is enabled (via the miscellaneous registers) the channel is powered only if the required power is within the remaining power budget; the channel can be powered regardless of the power-check availability via registers. if the power availability check has a positive result (or it hasn?t been performed), the channel is powered. otherwise, it is rejected, and the alarm flag raised in the channel events register. the channel number is registered into a scheduler fifo so that power will again be available when the channel is ready to be switched-on. figure 4. detection and classification equivalent architecture detection/cl ass ific a tion +4 8 v + - + + - 12- b it a/d converter digit a l controller + - d1 x12 d2 x12 s te12p s vl s p x p x +4v + 8 v + 17v - idet_hvlv 1 8 0pf detection/cl ass ific a tion + - + + - 12- b it a/d converter digit a l controller + - d1 x12 d2 x12 vl s p x p x +4v 8 v + 17v - idet_hvlv 1 8 0pf obsolete product(s) - obsolete product(s)
functional description STE12PS 14/44 3.3 power on after the classification phase the port will be powered. once activated, the power-on sequencer manages the channel?s activation requests received through the signature detection circuitry. for the incoming channel, activation requests are stored in the power-on sequencer and then serviced, one at a time, only when the previously activated channel leaves the current limiting condition that normally occurs during power on due to the capacitive part of the load. (see also smart-power mode and special issues) a port is turned-on by ramping-up the voltage and increasing the current limit to its upper limit. after a programmable time (t inrush ), if the port has reached full voltage and is out of current limitation, it is marked as powered. the related port power bit and the power class bits are set according to the class in the logic interface bit stream. the active ports are continuously monitored in order to detect a fault condition such as short circuit, disconnection or excess power (overload). 3.3.1 under load (disconnection) detection of a disconnection, if enabled (default condition), can be performed via a dc and/or ac method - default is dc ac (logical or): dc method if this method is selected via the logic interface and if the port current drops under 7.5ma for more than 10ms, then the STE12PS will detect a dc disconnection. if this condition persist for tmpdo ( ta bl e 1 2 ), then power is removed and the port is marked as free, enabling a new detection. ac method if this method is selected via the logic interface, the STE12PS probes the channels via coupling capacitors and detects when the ac load impedance, z ac , exceeds the maximum, 100k limit for a time longer than 20ms. in this case, the pse will detect an ac disconnection. if this condition persist for a time tmpdo ( ta bl e 1 2 ), power is removed and the port is marked as free, enabling a new detection. disconnection modes are as following: disabled, dc method only, ac method only, both ac and dc (combined in or logic or in and ? logic). obsolete product(s) - obsolete product(s)
STE12PS functional description 15/44 figure 5. power on and monitoring 3.3.2 short circuit, overload and overcurrent a short circuit is defined when port current reaches 425ma, typ. moreover, if port voltage drops below 25v, then maximum loop current is decreased, linearly, to limit power dissipation. a short condition is considered as a fault after a period of 65ms, typ. (see table 12: electrical characteristics , parameter tshort). when the above conditions are met, the port is disconnected, and the fault bit set high in the channel event registers. overload or excess power is defined when port power consumption reaches 15.4w for longer than 65ms, typ. (see table 12: electrical characteristics , parameter tovld). if smart-power management is active, then the overload power limit is set instead - according to the power class. when the above conditions are met, the port is disconnected, and the fault bit is set high. 12- b it a/d converter digit a l controller d1 x12 d2 x12 s te12p s vl p x f s rp x power on ctrl inru s hcurrent limitin g ss rp x + - power en s hort fl a g rmon s rmonf hqgnd ac di s connect detector ~ 50hz 5vpp ac_di s con fl a g ac s x s p x 3 00nf x12 power dmo s x12 rmon ( 500xr s en s e) r s en s ex12 (0.5, 1, 1 . 5, 2 ) +4 8 v 12- b it a/d converter 12- b it a/d converter digit a l controller digit a l controller d1 x12 d2 x12 s te12p s vl p x f s rp x power on ctrl inr us hc u rrent limiting ss rp x + - power en s hort fl a g rmon s rmonf hqgnd ac di s connect detector ~ 50hz 5vpp ac_di s con fl a g ac s x s p x 3 00nf x12 power dmo s x12 rmon ( 500xr s en s e) r s en s ex12 (0.5, 1, 1 . 5, 2 ) obsolete product(s) - obsolete product(s)
functional description STE12PS 16/44 monitor overload fsm this fsm manages all operations related to monitoring an overload event. all operations described below are related to channels currently powered. startup: the following operations are related to a startup procedure: ? start: channel to be monitored is selected. power measurement: the following operations are related to a power measurement procedure ? sample imeas: the current measurement is sampled and the next powered channel is prepared for the next monitor procedure. ? measure power: the power is measured and its value is compared against the required power class. ? start monitor overload: if the measured power exceeds the required power class the t ovld timer and the averaging process are started. ? counter reset: t ovld timer is reset if the measured power doesn?t exceed the required power removal: the following operations are related to a power removal procedure: ? counter check: all t ovld timers are checked, and those that have expired are identified. ? power removal: all the channels whose timers have expired and whose average power exceeds the maximum are switched off through the power_en(n) pins. ? alarm set: for all the channels whose timers have expired, a corresponding alarm flag is raised in the channel event registers, and the related ted timer is started. obsolete product(s) - obsolete product(s)
STE12PS functional description 17/44 monitor overcurrent fsm this particular fsm manages all operations related to procedures that are able to monitor an overcurrent event. all operations described below are related to channels currently powered. startup: ? start: the channel to be monitored is selected. voltage battery: ? sample v bat : every 12 channels cycle the v bat measurement is executed. overcurrent check: the following operations are related to an overcurrent check ?i meas check: if i meas >i lim the i_lim_flag is raised and the next powered channel is prepared for the next monitor procedure. ? start monitor: the t lim counter is started if i_lim_flag is found asserted. ? counter reset: if i_lim_flag is found de-asserted t lim counter is reset taking into account that glitches of duration less than 10ms are filtered. power removal: the following operations are related to a power removal operation: ? counter check: all the t lim timers are checked and those expired are identified. ? power removal: all the channels whose timer is expired are switched off. ? alarm set: for all the channels whose timers are expired a corresponding alarm flag is raised in the fault_event_chn register and the related ted timer is started. 3.3.3 thermal monitoring the procedures performed by the digital controller are impacted by the thermal monitoring data indicating the measured temperature. its behavior is based on a three-level control system : 1. when the chip's internal temperature reaches 110c, only the channels already powered will be serviced. possible new ones, will be rejected, redetected and eventually processed when the internal temperature cools down to 100c. this behavior can be disabled setting the proper bit register. 2. a second temperature threshold is set at 130c. when this value is reached, the channels that are in current limiting or inrush condition are immediately switched off, and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has cooled down to 100c. this behavior can be disabled by setting the proper bit register. 3. the third temperature threshold is set at 150c. when this temperature is reached, all activated channels will be immediately switched off, and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has decreased to 100c. this behavior cannot be disabled. obsolete product(s) - obsolete product(s)
functional description STE12PS 18/44 3.4 internal 3.3v/10v generator the STE12PS can be configured either as 3.3v and 10v generator or load by means of the s/u control input. in this manner, the need for extra, low-voltage batteries is avoided, greatly simplifying the system design. if s/u is left open, the device will operate as an smps controller. with the smps configured at 3.3v, the device can be used to power up a ?1amp? load with high efficiency voltage conversion. figure 6 on page 19 shows a typical dc-dc, buck converter configuration for the 3.3v supply. the 10v supply is generated by means of an internal, linear regulator. the 3.3v supply can source up to 1a. in figure 7 , use of a small transformer for the 10v supply can save up to 0.3w for each powered device. both the 3.3v and 10v supplies can power others devices. figure 8 depicts a typical application with an external supply. 3.5 logic interface the STE12PS can operate autonomously - notifying, externally, ports status via dedicated pins (parallel monitor interface) - or it can be controlled as a slave device via the i 2 c interface by a host processor. in the latter case, the host can perform system configurations, monitor status conditions and assert alarm flags making it possible to drive, manually, different operations for detection, classification and monitoring. obsolete product(s) - obsolete product(s)
STE12PS functional description 19/44 figure 6. simple smps +4 8 v v10 v 3 . 3 fb rlim vdrive ext low co s t pmo s e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen to other device s intern a lline a r reg u l a tor s /upin +4 8 v s te12p s v10 v 3 . 3 fb rlim vdrive ext low co s t pmo s e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen clock gen to other device s intern a lline a r reg u l a tor s /upin obsolete product(s) - obsolete product(s)
functional description STE12PS 20/44 figure 7. advanced smps +4 8 v v10 v 3 . 3 fb rlim vdrive e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen to other device s s /upin s te12p s v10 v 3 . 3 fb rlim vdrive e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen clock gen to other device s s /upin . obsolete product(s) - obsolete product(s)
STE12PS functional description 21/44 figure 8. with external power supplies 3.6 6mhz clock generator figure 10 on page 23 , and figure 11 and figure 12 on page 24 show the three possible clock generation configurations: a) with a 6mhz crystal for a high precision clock, b) with an external rc for low-cost applications, c) with an external clock. 3.7 smart-power mode when this mode is enabled, the whole system is set to manage and deliver a limited amount of power to the channel. in auto mode, it is actually possible to set a maximum power budget for the device. when a pd is connected to a port, the STE12PS verifies the class and decides to power the line only if there?s enough power available. it is also possible to set different priorities for the different channels. the device probes channels starting with those of highest priority. in case of shortage of available power, it is possible to disable the powering of newly detected ports of lower priority until the ones with a higher detected priority are serviced. if a channel exceeds its power class, that channel can be powered- down, and its power made available again. a 12-bit adc is used to provide high-quality voltage and current measurements during the various phases of port detection, +4 8 v vl v10 v 3 . 3 fb rlim vdrive e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen. +10v option a l + 3 . 3 v s /upin s te12p s vl v10 v 3 . 3 fb rlim vdrive e/a c u rrent limiting pmo s driver pwm & r a mp gener a tor s oft s t a rt s oft s t a rt b a ndg a p& reference s ft s tr rref1 vl s mp s clock gen. clock gen. s /upin obsolete product(s) - obsolete product(s)
functional description STE12PS 22/44 classification and powering. these measurements can be loaded into dedicated registers via the i 2 c bus and are intended to be averaged over time in order to maximize pssr and noise rejection as well as minimize 50 to 60hz interference. 3.8 power boost mode - 30w 3.8.1 four channels in auto mode when this mode is activated, the device will run the classification extending the ieee classes with an extra pd_class boost as detailed in ta b l e 4 . if class boost is detected, an equivalent double port (parallel of two channels) is switched-on allowing up to 30w of power to be supplied. all the other ieee classes behave as a standard port (powering on one channel only). ta b l e 5 below describes channel parallelism: channels in boost mode behave as master or slave according to the above table. detection and classification are performed only on the master ports. if a class 0 to 4 pd is detected, only mc is powered. otherwise, if boost class is detected, both mc and the related sc are powered. once powered, any fault condition (short circuit, over current, over power, pd disconnection) occurring either for mc or sc forces the reaction of both channels. all status and measurement information are stored in registers pertaining to the mc. detection procedure is the same as the standard one while the classification phase is performed with 3 classification impulses (total classification time 70ms). 3.8.2 six channels in manual mode to activate this mode the device should be set with ch_numx ="00" and the manual mode must be selected. under these conditions the output channels can be shorted together as illustrated in figure 9 and according to the following table. table 5. power boost mode: master/slave channel parallelism master channel (mc) slave channel (sc) 15 26 37 48 table 6. power boost mode: master/slave channel parallelism master channel (mc) slave channel (sc) 15 26 37 48 912 10 11 obsolete product(s) - obsolete product(s)
STE12PS functional description 23/44 all the functions that manage the six "boost" channels must be implemented by an external microcontroller. figure 9. power boost mode figure 10. crystal oscillator det/cl ass +4 8 v 12- b it a/d converter digit a l controller d1 x12 d2 x4 vl power-on ctrl, inr us hc u rrent limiting ss rp s c + - power en s hort fl a g rmon s rmonf hqgnd ac di s connect detector ~ ac_di s con fl a g ac s mc s p mc 3 00nf x4 power dmo s x 8 rmon ( 500xr s en s e) ss rp mc mc s c r s en s e det/cl ass det/cl ass 12- b it a/d converter 12- b it a/d converter digit a l controller digit a l controller d1 x12 d2 x4 s te12p s vl power-on ctrl, inr us hc u rrent limiting ss rp s c + - power en s hort fl a g rmon s rmonf hqgnd ac di s connect detector ~ ac_di s con fl a g ac s mc s p mc 3 00nf x4 power dmo s x 8 rmon ( 500xr s en s e) ss rp mc mc s c r s en s e mclko u tclkgen1 clkgen2 clkgen 3 16pf 16pf 6mhz cry s t a l s te12p s mclko u tclkgen1 clkgen2 clkgen 3 16pf 16pf 6mhz cry s t a l obsolete product(s) - obsolete product(s)
functional description STE12PS 24/44 figure 11. low cost rc oscillator figure 12. with external oscillator mclko u tclkgen1 clkgen2 clkgen 3 210pf 8 20 ohm s te12p s mclko u tclkgen1 clkgen2 clkgen 3 210pf 8 20 ohm mclko u tclkgen1 clkgen2 clkgen 3 s te12p s mclko u tclkgen1 clkgen2 clkgen 3 extern a l6mhz obsolete product(s) - obsolete product(s)
STE12PS functional description 25/44 3.9 measurement and parameter codings ta b l e 7 below lists codifications for the various parameters such as detection conductance or resistances, classification or monitoring currents, port voltages, port powers and power budgets. table 7. measurement and parameter codings parameter description range step units number of steps idet detection current 0 to 1023 1 a 1024 gdet, gdl, gdh detection conductances 0 to 256 0.250 s 1024 rdet, rdl, rdh (1) detection residences 8 to 48.96 0.01 k ? 4096 iclass current classification 0 to 70 0.065064 ma 1024 imon channel current during powering 0 to 1024 0.0312662 ma 32768 vport battery voltage 0 to 70 0.27451 v 256 pmeas channel power usage 0 to 35000 35.149 mw 1024 1. rdet, rdl and rdh are the alternative to gdet, gdl and gdh wh ich are the default. if rdet measures more than 500kohms, the ?open-circuit? flag is raised, that is set high. obsolete product(s) - obsolete product(s)
i2c interface STE12PS 26/44 4 i2c interface the STE12PS has an i2c interface to allow the access to the internal device registers. the external controller can be fully isolated from the ethernet port thanks to an integrated 3.3v smps power source and using optocouplers on i2c bus.( figure 13 ). figure 13. isolated ethernet power system using optocouplers for i 2 c interface s dain s daout s clin dgnd opc 1 opc 3 3 . 3 v digit a lgro u nd s cl bus s da bus controller gnd controller vdd intn int bus opc 2 opc 4 s dain s daout s clin dgnd opc 1 opc 3 3 . 3 v digit a lgro u nd s te12p s s cl bus s da bus controller gnd controller vdd intn int bus opc 2 obsolete product(s) - obsolete product(s)
STE12PS i2c slave protocol overview 27/44 5 i 2 c slave protocol overview the interface is capable of recognizing its own address (7 bit). data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condition contains the device address. a 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must pull low the sda line to acknowledge the transfer. the speed of the i 2 c interface is fixed at fast i 2 c, that is, 100 to 400khz. 5.1 functional description as soon as a start condition is detected, the address is received from the sda line and sent to a shift register; then it is compared with the internal address that is composed by the five pins for the five lsb and by a hardwired value equal to ?01? for the other two bits. in case of address mismatch the interface ignores it and waits for another start condition. if address is matched the interface generates an acknowledge pulse. following the address reception, poe digital controller receives bytes from the sda line into the data register via an internal shift register or sends bytes from the data register to the sda line through the internal shift register. after each byte reception an acknowledge pulse is generated by the controller. a stop condition generated by the host processor, after the last data byte is transferred, closes the communication. 5.2 error cases an error state is generated when stop or start conditions are detected during a byte transfer. if it is a stop then the interface discards the data, releases the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. 5.3 interrupts irq register bits indicate which signals can generate an interrupt. the register is read only and to clear the interrupt bits the corresponding source event has to be cleared. the logic or condition of the interrupt bits causes the intn pin assertion. the intn assertion can be masked via the interrupt mask register irq_mask . 5.4 i 2 c device address the device is required to have an i 2 c address of: 01xxxxxb(a6 down to a0). pins i2c_addr[4:0] can be used to set the lower i 2 c address bits. obsolete product(s) - obsolete product(s)
i2c slave protocol overview STE12PS 28/44 5.5 register addressing: write command format i 2 c write command format is shown in figure 14 . figure 14. write command the formatting bits shown in figure 14 are defined as follows: s - i 2 c start condition p - i 2 c stop condition ack ? acknowledge nack - not acknowledge r/w - read/write the device address is the value specified in i 2 c device address. the register address is an eight-bit value that is written into an internal index register. each time a byte of data is written to, or read from the poe controller, the index register increments by one. if the initial value written to the index register is k, then the byte immediately following the register address byte is written to the register with an address of k. the next byte is written to the register with the address of k+1, and so on. an i 2 c write command can contain from 0 to 255 write data bytes. write commands to an unknown register location are ignored by the interface. as shown in figure 14 , bits are ordered with the most significant bit first. s 6 54 32 1 0 device address w r/w ack 7 . register address (k) ack 6543210 7 6 54 32 1 0 write data ack 7 . write data (k + 1) ack 6543210 7 6 54 32 1 0 write data (k + n) p ack obsolete product(s) - obsolete product(s)
STE12PS i2c slave protocol overview 29/44 5.6 register addressing: read command format the general format of the read command is shown in figure 15 . first part of the general read command consists of writing an address to the index register of the poe controller. if the index register already contains the address of the register to be read, as the result of a previous read or write command, then it is not necessary to write that address to the index register again. after each byte is read from the poe controller, the index register is required to increment by one. a read command can contain from 0 to 255 bytes. figure 15. read command s 6 54 32 1 0 device address w r/w ack 7 . register address (k) ack 6543210 p s 6 54 32 1 0 device address r r/w ack 7 . read data (k) ack 6543210 7 6 54 32 1 0 read data (k + 1) ack 7 read data (k + 2) ack 6543210 7 6 54 32 1 0 read data (k + n) ack p obsolete product(s) - obsolete product(s)
i2c slave protocol overview STE12PS 30/44 5.7 parallel monitoring interface in order to monitor the status of the different ports without the i 2 c register addressing, a simple, output status interface has been implemented. this digital interface is comprised of 9 output pins: ch_sel[3:0], pok, ovld, ovcur, ac_dc_discon and det_class. bits ch_sel[3:0] indicate the channel status flags (pok,..., det_class) that are currently notified, externally. ch_sel is incremented every 60mclk clock cycles. pok stands for power ok. when high, it indicates that the channel is currently powered-on in normal condition. ovld stands for overload and indicates a faulty condition due to abnormal power dissipation (more than pclass) of a powered channel. ovcur stands for overcurrent, and it highlights a channel whose current has reached the power-on current limit of 425ma (typ. value). bit ac_dc_discon goes high when a powered channel fails in providing a correct mps (maintain power signature). this typically happens when a pd is disconnected from the line. det_class indicates a situation where a channel is not yet powered and whose ?signature? is currently being probed. status flag notification is enabled by bit status_flag_en of the configuration register global_cfg2. by default this bit is high, that is, enabled. this information is particularly useful in simple applications without a microprocessor or for testing purposes. another use is to easily build-up an led graphical interface showing runtime status of the various channels. obsolete product(s) - obsolete product(s)
STE12PS electrical specifications and timings 31/44 6 electrical specifications and timings table 8. absolute maximum ratings symbol parameter value units v l , smpsv l battery voltage 90 v vcc3,vdd,vdde 3.3v power supply 3.6 v v10,vdd10 10v power supply 12 v tj maximum junction temperature 150 c table 9. operating range symbol parameter value units t opt operating temperature range -20 to +85 c v l , smpsv l battery voltage 44 to 57 v gnds ground separation -0.3 v vcc3, vdd, vdde 3.3v when externally supplied 3 to 3.6 v v10, vdd10 10v when externally supplied 9 to 11 v i v10 , i vdd10 10v current sink (when externally supplied) 6.7 typ. ma i vl battery current sink (when 10v is externally supplied) 0.4 typ. ma i vl battery current sink (when 10v is self generated) 7.4 typ. ma i v3.3 3.3v current sink (auto mode) 20 typ. ma table 10. thermal data symbol parameter value units r th j-amb thermal resistance junction-to-ambient (natural convection) 25 c/w table 11. esd symbol parameter value units hbm (human body model) all pins but pins px_1-2 & px_3 -2 to +2 kv all pins but pins fsrpx_1-2 & px_3 (x = 1 to 12) pins px_1-2 & px_3 -250 to +250 v pins fsrpx_1-2 & px_3 (x = 1 to 12) obsolete product(s) - obsolete product(s)
electrical specifications and timings STE12PS 32/44 cdm (charge device model) corner pins -750 to +750 v all pins but pins px_1-2 & px_3 -500 to +500 v all pins but pins fsrpx_1-2 & px_3 (x = 1 to 12) pins px_1-2 & px_3 -250 to +250 v pins fsrpx_1-2 & px_3 (x = 1 to 12) mm (machine model) all pins but pins px_1-2 & px_3 -200 to +200 v all pins but pins fsrpx_1-2 & px_3 (x = 1 to 12) pins px_1-2 & px_3 -50 to +50 v pins fsrpx_1-2 & px_3 (x = 1 to 12) table 11. esd (continued) symbol parameter value units table 12. electrical characteristics symbol parameter min. typ. max. units notes detection vdl detection voltage low level 3.7 4 4.3 v between port terminals vdh detection voltage high level 7.4 8 8.6 v between port terminals tds transient time between vdl and vdh 300 s adjustable with external capacitor cdetslow gdl conductance signature, lower limit (software programmable) 25 50 mhos software programmable) gdh conductance signature, upper limit (software programmable) 41 82 mhos software programmable rdl resistance signature, lower limit (software programmable) 12 24 k software programmable, to be used as an alternative to gdh rdh resistance signature, upper limit (software programmable) 20 40 k software programmable, to be used as an alternative to gdl idlim current limit during detection 1.1 ma tdet detection time 50 ms 12-port configuration, one channel at a time tdetd detection delay time (from pd insertion to end of detection phase) 852 ms maximum delay for 12- port configuration tdbo back-off time (midspan mode) 2 sec. back off time in case of failed pd detection, avoided if rdet > 500k or gdet < 2mhos ted error delay time 750 ms obsolete product(s) - obsolete product(s)
STE12PS electrical specifications and timings 33/44 classification vcl classification probing voltage 15.9 17 18.1 v between port terminals icllim current limit during classification 55 70 ma tcl classification time 15 ms one channel at a time, classification measurement has to be considered as sampled and integrated over this time interval. ithcl0 class0-1 current threshold 5.5 6.5 7.5 ma ithcl1 class1-2 current threshold 13.5 14.5 15.5 ma ithcl2 class2-3 current threshold 21.8 23 24.2 ma ithcl3 class3-4 current threshold 31.5 33 34.5 ma ithcl4 class4-0 current threshold 45.5 46.5 47.5 ma powering pall maximum power per channel 15.4 w see also classification paragraph (doubled in case of boost configuration) iinrush output current startup mode 400 450 ma inrush current soft start imin power off current 5 10 ma disconnect for t > tpmdo (dc disconnection method) acfre ac disconnection sinusoidal generator 50 hz frequency spread related to clock stability vacd ac generator open line voltage 2.5 v pp zac ac impedance needed to maintain power 100 k tmpdo pd power maintenance request drop out time limit (software programmable) 300 400 ms the STE12PS will not remove power if the pd maintenance signal is absent for less than 300ms duration. if an absence of power maintenance signal has been detected, the STE12PS shall remove power within 400ms max (1) icut over load current pall/vport 400 ma after time duration of tovld the STE12PS will disconnect the power from the port. table 12. electrical characteristics (continued) symbol parameter min. typ. max. units notes obsolete product(s) - obsolete product(s)
electrical specifications and timings STE12PS 34/44 to v l d over load time limit (software programmable) 50 65 75 ms in fault condition for tovld, the STE12PS will disconnect the port . (1) tshort short-circuit/inrush time limit (software programmable) 50 65 75 ms i n fault condition for tshort, the STE12PS will disconnect the port. (1) i lim output load current under short - circuit condition 400 450 ma max. value of port current during short circuit condition. power will be disconnected from the port within tshort tinrush rise time of vport time limit 75 ms expired tinrush if the channel is still in limiting condition it is considered in fault toff turn off time 100 ms from vport to 2.8v dc ron internal mosfet resistance in on mode 1ohms vslr 3v range in generator mode 3 3.3 3.6 v v10 int 10v range internally generated 8.7 v digital fclk clock frequency 6 mhz v ih input high level voltage 2 v @ v dd = 3.3v v il input low level voltage 0.8 v @ v dd = 3.3v i ih input high current 30 a i il input low current 10 a 1. see also timer programmability table 12. electrical characteristics (continued) symbol parameter min. typ. max. units notes obsolete product(s) - obsolete product(s)
STE12PS ball coordinates 35/44 7 ball coordinates figure 16. balls top view layout (as viewed through package) view through package 12 3 4567 8 9 1011121 3 14 15 16 17 1 8 19 20 21 22 a ch_ s el0 ch_ s el1 ovld s cl intn s dain s daout ch_num1 ch_num0 agnd idet_hvl v i_ref v ba tref agnd re s etn porn vdde gnde vdd power_e n0 power_e n1 power_e n2 b ch_ s el2 ch_ s el 3 ac_dc_di s con det_cla s s i2c_addr 0 i2c_addr 1 i2c_addr 2 te s t_mo de1 te s t_mo de0 agnd agnd imon_hvl v v ba tmon agnd vdde vdde gnde vdd gnd power_e n 3 power_e n4 power_e n5 c vdd10 v10 v 3 _ 3 pok ovcur i2c_addr 3 i2c_addr 4 a_bn_ s el auto_ s t art s can_en agnd agnd agnd agnd vdde gnde vdd gnd gnd power_e n6 power_e n7 power_e n 8 d s mp s gnd s ft s tr acin aco u t gnd clk_gen1 clk_gen2 mclko u t clk_gen 3 vdda gnd gnd gnd gnde gnde vdd vdd gnd gnd power_e n 9 power_e n10 power_e n11 e s /u nc rref gnd gnd cdet s low nc nc f nc nc fb gnd rmon s rmonf nc p 8 _1-2 g s en s er nc s en s eprog pin0 dgnd hqgnd f s rp 8 _1-2 nc p 8 _ 3 h vdrive nc s en s eprog pin1 dgnd ac s8 f s rp 8 _ 3 nc s p 8 j c n c n 4 s c a 8 p r s s d n g d n g d n g d n g d n g d n g d n g 5 s c a c n l v s p m s k 2 - 1 _ 4 p c n 2 - 1 _ 4 p r s f 4 p r s s d n g d n g d n g d n g d n g d n g d n g 5 p r s s c n l v l 3 _ 4 p c n 3 _ 4 p r s f d n g d n g d n g d n g d n g d n g d n g d n g 2 - 1 _ 5 p r s f c n c n m 4 p s c n 2 1 s c a d n g d n g d n g d n g d n g d n g d n g d n g 3 _ 5 p r s f c n 2 - 1 _ 5 p n c n c n 2 1 p r s s d n g d n g d n g d n g d n g d n g d n g d n g 1 s c a c n 3 _ 5 p p d n g d n g d n g d n g d n g d n g d n g d n g 1 p r s s c n 5 p s f s rp12_1- 2 nc p12_1-2 r nc nc f s rp1_1-2 gnd gnd f s rp12_ 3 nc p12_ 3 t p1_1-2 nc f s rp1_ 3 gnd gnd ac s 7nc s p12 u p1_ 3 nc ac s9 gnd gnd ss rp7 nc nc v s p1 nc ss rp 9 gnd gnd f s rp7_1-2 nc p7_1-2 w nc nc f s rp 9 _1-2 gnd ss rp6 gnd gnd ss rp2 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ss rp 3 f s rp7_ 3 nc p7_ 3 y p 9 _1-2 nc f s rp 9 _ 3 ac s 6f s rp6_1-2 f s rp6_ 3 ac s 2f s rp2_1-2 f s rp2_ 3 ac s 10 ss rp10 f s rp10_1- 2 f s rp10_ 3 f s rp11_1- 2 f s rp11_ 3ss rp11 ac s 11 f s rp 3 _ 3 f s rp 3 _1-2 ac s3 nc s p7 aa p 9 _ 3 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ab s p 9 nc p6_1-2 p6_ 3s p6 nc p2_1-2 p2_ 3s p2 nc p10_1-2 p10_ 3s p10 nc s p11 p11_ 3 p11_1-2 nc s p 3 p 3 _ 3 p 3 _1-2 nc obsolete product(s) - obsolete product(s)
ball coordinates STE12PS 36/44 table 13. pad coordinates column row pin name column row pin name 1 a ch_sel0 2 p nc 1 aa p9_3 3 m fsrp5_3 1 ab sp9 3 n acs1 1 b ch_sel2 2 r nc 1 c vdd10 2 t nc 1 d smpsgnd 2 u nc 1e s/u 2v nc 1f nc 2w nc 1 g rsense 2 y nc 1h vdrive 2aa nc 1 j smpsvl 2 ab nc 1k vl 3a ovld 1 l nc 3 b ac_dc_discon 1 m p5_1-2 3 c v3_3 1n p5_3 3d acin 1p sp5 3e rref 1r nc 3f fb 1 t p1_1-2 3 g senseprogpin0 1 u p1_3 3 h senseprogpin1 1 v sp1 3 j acs5 1 w nc 3 k ssrp5 1 y p9_1-2 3 l fsrp5_1-2 2 a ch_sel1 3 p ssrp1 2 b ch_sel3 3 r fsrp1_1-2 2 c v10 3 t fsrp1_3 2d sftstr 3u acs9 2e nc 3v ssrp9 2 f nc 3 w fsrp9_1-2 2 g nc 3 y fsrp9_3 2h nc 3aa nc 2 j nc 3 ab p6_1-2 2k nc 4a scl 2 l nc 4 b det_class 2m nc 4c pok 2n nc 4d acout obsolete product(s) - obsolete product(s)
STE12PS ball coordinates 37/44 4 aa nc 9 b test_mode0 4 ab p6_3 9 c auto_start 4 e gnd 7 b i2c_addr2 4 f gnd 7 c i2c_addr4 4 g dgnd 7 d clk_gen2 4 h dgnd 7 w gnd 4j gnd 7y acs2 4k gnd 7aa nc 4 l gnd 7 ab p2_1-2 4 m gnd 8 a ch_num1 4 n gnd 8 b test_mode1 4 p gnd 8 c a_bn_sel 4r gnd 8d mclkout 4 t gnd 8 w ssrp2 4 u gnd 8 y fsrp2_1-2 4v gnd 8aa nc 4 w gnd 8 ab p2_3 4 y acs6 9 a ch_num0 5a intn 9dclk_gen3 5aa nc 9 p gnd 5 ab sp6 9 w gnd 5 b i2c_addr0 9 j gnd 5 c ovcur 9 k gnd 5 d gnd 9 l gnd 5 w ssrp6 9 m gnd 5 y fsrp6_1-2 9 n gnd 6 a sdain 9 y fsrp2_3 6aa nc 10d vdda 6ab nc 10 j gnd 6 b i2c_addr1 9 aa nc 6 c i2c_addr3 9 ab sp2 6 d clk_gen1 10 a agnd 6w gnd 10b agnd 6 y fsrp6_3 10 c scan_en 7a sdaout 10k gnd table 13. pad coordinates (continued) column row pin name column row pin name obsolete product(s) - obsolete product(s)
ball coordinates STE12PS 38/44 10 aa nc 13 k gnd 10 ab nc 13 l gnd 10 l gnd 12 ab p10_3 10 m gnd 13 a vbatref 10 n gnd 13 b vbatmon 10 p gnd 13 c agnd 10 w gnd 13 d gnd 10 y acs10 13 j gnd 11 a idet_hvlv 13 m gnd 11 aa nc 14 k gnd 11 ab p10_1-2 14 l gnd 11 b agnd 13 n gnd 11 c agnd 13 p gnd 11 d gnd 13 w gnd 11 j gnd 13 y fsrp10_3 11 k gnd 13 aa nc 11 l gnd 13 ab sp10 11 m gnd 14 a agnd 11 n gnd 14 b agnd 11 p gnd 14 c agnd 11 w gnd 14 d gnde 11 y ssrp10 14 j gnd 12 a i_ref 14 m gnd 12 aa nc 15 y fsrp11_3 12 b imon_hvlv 14 n gnd 12 c agnd 14 p gnd 12 d gnd 14 w gnd 12 j gnd 14 y fsrp11_1-2 12 k gnd 14 aa nc 12 l gnd 14 ab nc 12 m gnd 15 a resetn 12 n gnd 15 b vdde 12 p gnd 15 c vdde 12 w gnd 15 d gnde 12 y fsrp10_1-2 15 w gnd table 13. pad coordinates (continued) column row pin name column row pin name obsolete product(s) - obsolete product(s)
STE12PS ball coordinates 39/44 15 aa nc 19 k ssrp4 15 ab sp11 19 l gnd 16 a porn 19 m gnd 16 aa nc 19 v gnd 16 ab p11_3 19 w ssrp3 16 b vdde 19 n gnd 16 c gnde 19 p gnd 16 d vdd 19 r gnd 16 w gnd 19 t gnd 16 y ssrp11 19 u gnd 17 a vdde 19 y fsrp3_1-2 17 aa nc 20 d power_en9 17 ab p11_1-2 20 e cdetslow 17 b gnde 19 aa nc 17 c vdd 19 ab sp3 17 d vdd 20 a power_en0 17 w gnd 20 b power_en3 17 y acs11 20 c power_en6 18 a gnde 20 f rmonf 18 aa nc 20 m acs12 18 ab nc 20 n ssrp12 18 b vdd 20 g fsrp8_1-2 18 c gnd 20 h fsrp8_3 18 d gnd 20 j acs4 18 w gnd 20 k fsrp4_1-2 18 y fsrp3_3 20 l fsrp4_3 19 a vdd 20 p fsrp12_1-2 19 b gnd 20 r fsrp12_3 19 c gnd 20 t acs7 19 d gnd 20 u ssrp7 19 e gnd 20 v fsrp7_1-2 19 f rmons 20 w fsrp7_3 19 g hqgnd 20 y acs3 19 h acs8 20 aa nc 19 j ssrp8 20 ab p3_3 table 13. pad coordinates (continued) column row pin name column row pin name obsolete product(s) - obsolete product(s)
ball coordinates STE12PS 40/44 21 a power_en1 22 r p12_3 21 ab p3_1-2 22 t sp12 21 b power_en4 22 u nc 21 c power_en7 22 v p7_1-2 21 d power_en10 22 w p7_3 21 e nc 22 y sp7 21 f nc 22 aa nc 21 g nc 22 ab nc 21 h nc 21 j nc 21 k nc 21 l nc 21 m nc 21 n nc 21 p nc 21 r nc 21 t nc 21 u nc 21 v nc 21 w nc 21 y nc 22 a power_en2 22 b power_en5 22 c power_en8 22 d power_en11 22 e nc 22 f p8_1-2 22 g p8_3 22 h sp8 22 j nc 22 k p4_1-2 22 l p4_3 22 m sp4 22 n nc 22 p p12_1-2 table 13. pad coordinates (continued) column row pin name column row pin name obsolete product(s) - obsolete product(s)
STE12PS package information - mechanical data 41/44 8 package information - mechanical data in order to meet environmental requirements, st microelectronics offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st microelectronics trademark. ecopack specifications are available at: www.st.com. package code: tn jedec/eiaj reference number: jedec standard no. 95-1, section 14 (ball grid array package design guide) note: 1 maximum mounted height, dimension a, is 1.77mm based on a 0.35mm ball pad diameter. solder paste is 0.15mm thick and 0.35mm in diameter. 2 pbga stands for plastic ball grid array. 3 the terminal a1 corner must be on the top surface by using a corner chamfer, ink, metallized markings or some other feature of the package body or internal heatslug. 4 a distinguishing feature is allowed on the bottom surface of the package to identify terminal the a1 corner. 5 exact shape of each corner is optional. table 14. package dimensions ref. databook (mm) drawing (mm) min. typ. max. min. typ. max. a 1.720 1.620 1.720 1.820 a1 0.270 0.350 0.400 0.450 a2 1.320 1.320 b 0.450 0.500 0.550 0.450 0.500 0.550 d 22.800 23.000 23.200 22.900 23.000 23.100 d1 21.000 21.000 e 22.800 23.000 23.200 22.900 23.000 23.100 e1 21.000 21.000 e 0.950 1.000 1.050 0.950 1.000 1.050 f 0.875 1.000 1.125 0.875 1.000 1.125 ddd 0.200 0.200 obsolete product(s) - obsolete product(s)
package information - mechanical data STE12PS 42/44 figure 17. pbga23x23 package mechanical drawing obsolete product(s) - obsolete product(s)
STE12PS ordering information 43/44 9 ordering information 10 revision history table 15. order codes part number temperature range package e-STE12PS (1) 1. e-: ecopack ? -40c to +85 c pbga (23mm x 23mm x 1.82mm) table 16. document revision history date revision changes 10-nov-2006 1 initial release 13-dec-2006 2 updated the number of 30w boosted ports to be four or six instead of four previously (cover page and section 3.8 ). 17-aug-2007 3 added table 11: esd in chapter 6 . obsolete product(s) - obsolete product(s)
STE12PS 44/44 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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